Tap Mainboard
AssemblyThe copy engine: an FPGA or switch ASIC regenerates each direction of traffic to its monitor port at line rate without buffering-induced reordering, while an MCU runs link state and management. A full specification article for this item is being written. Meanwhile its bill of materials and connections are below.
Bill of materials for Tap Mainboard
6 top-level lines as of r59238| # | Item / sub-assembly | Part no. | Qty/assy | Ext. qty | Parts | Type |
|---|---|---|---|---|---|---|
| 1 | Bare PCB | pcb-bare | 1× | 1 | · | part |
| 2 | Tap FPGA | ethernet-tap-fpga | 1× | 1 | · | part |
| 3 | Microcontroller | mcu | 1× | 1 | · | part |
| 4 | Reference Oscillator | ethernet-tap-osc | 1× | 1 | · | part |
| 5 | Status LED | ethernet-tap-led-bank | 6× | 6 | · | part |
| 6 | SMD Passive (R/C/L) | smd-passives | 120× | 120 | · | part |