Packet Input Stage
AssemblyHigh-speed deserializers converting 100 Gbps QSFP28 streams to internal packet format, with buffer management. A full specification article for this item is being written. Meanwhile its bill of materials and connections are below.
Bill of materials for Packet Input Stage
5 top-level lines as of r114435| # | Item / sub-assembly | Part no. | Qty/assy | Ext. qty | Parts | Type |
|---|---|---|---|---|---|---|
| 1 | QSFP28 100 Gbps Port | network-packet-broker-qsfp28-port-x12 | 12× | 12 | · | part |
| 2 | Multi-Lane SerDes ASIC | network-packet-broker-serdes-asic | 1× | 1 | · | part |
| 3 | 64 GB Input Buffer DRAM | network-packet-broker-input-buffer | 1× | 1 | · | part |
| 4 | 256 MB Descriptor Cache SRAM | network-packet-broker-descriptor-cache | 1× | 1 | · | part |
| 5 | SMD Passive (R/C/L) | smd-passives | 2× | 2 | · | part |