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Decode Processor

Assembly

FPGA or specialized ASICs decode captured bits into human-readable protocol frames (I2C start condition, SPI transactions, CAN frames).

Direct parts	4
Class	Assembly

FPGA or specialized ASICs decode captured bits into human-readable protocol frames (I2C start condition, SPI transactions, CAN frames). A full specification article for this item is being written. Meanwhile its bill of materials and connections are below.

Bill of materials for Decode Processor

4 top-level lines as of r134070

#	Item / sub-assembly	Part no.	Qty/assy	Ext. qty	Parts	Type
1	Programmable FPGA	protocol-analyzer-fpga	1×	1	·	part
2	LUT Memory	protocol-analyzer-lookup-ram	2×	2	·	part
3	Frame Formatter	protocol-analyzer-frame-formatter	1×	1	·	part
4	Filter Logic	protocol-analyzer-filter-network	1×	1	·	part