Radio SoC
PartSingle chip combining a MIPS/ARM network processor with a 2x2 MIMO 5 GHz radio running a TDMA bridge protocol. A full specification article for this item is being written. Meanwhile its bill of materials and connections are below.
Single chip combining a MIPS/ARM network processor with a 2x2 MIMO 5 GHz radio running a TDMA bridge protocol. A full specification article for this item is being written. Meanwhile its bill of materials and connections are below.